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-----Original Message----- From: mi400-bounces@xxxxxxxxxxxx [mailto:mi400-bounces@xxxxxxxxxxxx]On Behalf Of Walden H. Leverich Sent: Monday, February 07, 2005 10:37 AM To: MI Programming on the AS400 / iSeries Subject: RE: [MI400] LQ and SELRI PowerPC instruction questions >>so the effective result of the LQ folowed by SELRI instructions is to >>load >>reg26 with either the address contents of the pointer or zero if the >>pointer >>is not valid. >So if I understand this correctly (which I probably don't <G>) the >"security" features of OS/400 are based in the translator which moves >from MI/NMI to PPC Risc, not in the chip itself. That is, you can remove >the check if you change the generated opcodes, yes? yes. dont tell anyone! -Steve -----Original Message----- From: mi400-bounces@xxxxxxxxxxxx [mailto:mi400-bounces@xxxxxxxxxxxx] On Behalf Of Steve Richter Sent: Monday, 07 February, 2005 10:12 To: MI Programming on the AS400 / iSeries Subject: RE: [MI400] LQ and SELRI PowerPC instruction questions -----Original Message----- From: mi400-bounces@xxxxxxxxxxxx [mailto:mi400-bounces@xxxxxxxxxxxx]On Behalf Of Gene_Gaunt@xxxxxxxxxxxxxxx Sent: Monday, February 07, 2005 9:30 AM To: MI Programming on the AS400 / iSeries Subject: Re: [MI400] LQ and SELRI PowerPC instruction questions On 10/30/2004 Steve Richter wrote: >> What is the 3rd operand of the LQ instruction used for? >> What is the SELRI instruction? >They appear to deal with an AS/400 extension to the powerPC 32-bit >exception register: the sixteen AS/400 exception bits 32 through 47. >LQ: RT,DQ(RA),PT >"PT" is an ORed mask of pointer type integrity checks to set AS/400 >exception bit 41: so LQ is hard coded to set exception register bit 41. >B'1000' = system pointer >B'0100' = instruction pointer >B'0010' = space pointer >B'0001' = data pointer >SELII: RT,IA,IB,XBI,rc >SELIR: RT,IA,RB,XBI,rc >SELRI: RT,RA,IB,XBI,rc >SELRR: RT,RA,RB,XBI,rc II = immed, immed IR = Immed, reg RI = Reg , Immed RR = Reg, Reg Any idea what the "SEL" mnemonic stands for? >The SELxx instructions test the AS/400 exception bit (32 through 47) named >in operand 4: if on, copy operand 2 into operand 1; if off, copy operand 3 >into operand 1. "IA" and "IB" are 5-bit signed immediate values, value >range -16 through +15. "RA" and "RB" are general purpose registers. "XBI" >is a 4-bit index into the sixteen AS/400 exception bits 32 through 47. (In >other words, add 32 to the "XBI" 4-bit value.) >For example: >LQ 24,0X1E50(30),6 >SELRI 26,25,0,41 >This means, >LQ: Copy the quadword at effective address (GPR30 + x"1E50") into GPR24 >and GPR25; if the pointer tag bit at effective address (GPR30 + x"1E50") is >on, AND if that quadword data is an instruction pointer (integrity check >B'0100') or a space pointer (integrity check B'0010'), then set on AS/400 >exception bit 41; otherwise, set off AS/400 exception bit 41. LQ tests both the tag bit, which is not a part of the 16 byte pointer, AND also some bits in the non address part of the pointer that indicate what type of pointer it is. >SELRI: Test AS/400 exception bit 41; if on, then copy GPR25 into GPR26; if >off, then copy x"0000000000000000" into GPR26. so the effective result of the LQ folowed by SELRI instructions is to load reg26 with either the address contents of the pointer or zero if the pointer is not valid. Very neat! Thanks Gene. -Steve _______________________________________________ This is the MI Programming on the AS400 / iSeries (MI400) mailing list To post a message email: MI400@xxxxxxxxxxxx To subscribe, unsubscribe, or change list options, visit: http://lists.midrange.com/mailman/listinfo/mi400 or email: MI400-request@xxxxxxxxxxxx Before posting, please take a moment to review the archives at http://archive.midrange.com/mi400. _______________________________________________ This is the MI Programming on the AS400 / iSeries (MI400) mailing list To post a message email: MI400@xxxxxxxxxxxx To subscribe, unsubscribe, or change list options, visit: http://lists.midrange.com/mailman/listinfo/mi400 or email: MI400-request@xxxxxxxxxxxx Before posting, please take a moment to review the archives at http://archive.midrange.com/mi400.
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