RE: [MI400] LQ and SELRI PowerPC instruction questions

["Steve Richter" <srichter@xxxxxxxxxxxxx>]

-----Original Message-----
From: mi400-bounces@xxxxxxxxxxxx [mailto:mi400-bounces@xxxxxxxxxxxx]On
Behalf Of Gene_Gaunt@xxxxxxxxxxxxxxx
Sent: Monday, February 07, 2005 11:04 AM
To: MI Programming on the AS400 / iSeries
Subject: Re: [MI400] LQ and SELRI PowerPC instruction questions

>By the way, for further insight into the SELxx instructions, look at the
>following RISC disassembly on V5R3 of the procedure "llabs" in module
>"QC2ABS" in service program "QSYS/QC2UTIL2".  This little procedure simply
>receives a values in GPR4 and returns its absolute value in GPR3:

>CMPI 0,1,4,0
http://www.nersc.gov/vendor_docs/ibm/asm/cmpi.htm#a28691b6

CMPI - compare immediate.
0 = place compare results in "field" 0 of the condition register. The 32 bit
condition register has 8, 4 bit, bit fields.  The bits of each field are LT,
GT, EQ, SO.
1 = use all 64 bits of the registers.  if 0, use 32 bits.
4 = reg04
0 = immediate value 0.

This instruction compares 0 to the full 64 bits of reg4 and places the
LT/GT/EQ/SO result of the compare in field 0 of the condition register.

>NEG 0,4

http://www.nersc.gov/vendor_docs/ibm/asm/neg.htm#etp12d0ken

negate reg04 and place the results in reg00.

note that the ".neg" version of the "neg" instruction will set bit field 0
of the condition register with the LT/GT/EQ/SO result of the instruction.

so:
  CMPI 0, 1, 4, 0
  NEG  0, 4

might be the same as:
  NEG. 0, 4

The CMPI instruction might not be necessary.  So much for the patent
protected IBM PowerPC optimizing compiler!

>SELRR 0,0,4,36
>ORI 3,0,0
>BCLR 20,0

>Here it appears that AS/400 exception bit "36" is a copy of a standard
>PowerPC bit in condition register 0 (Positive, Negative, or Zero).

Which would be the LT bit of Field 9. Bits 36 - 39 of the condition
register.  Guessing here, field 0 of the condition register has a special
quality in that a lot of PPC instructions have a "." version which update
field 0 of the condition register with the LT/GT/EQ results of the
instruction. Possibly any change to field 0 ( bits 0 - 3 ) of the condition
register is also applied to field 9 ( bits 36 - 39 ) of the condition
register.

-Steve