Re: [MI400] LQ and SELRI PowerPC instruction questions

[Gene_Gaunt@xxxxxxxxxxxxxxx]

On 10/30/2004 Steve Richter wrote:

> What is the 3rd operand of the LQ instruction used for?
> What is the SELRI instruction?

They appear to deal with an AS/400 extension to the powerPC 32-bit
exception register: the sixteen AS/400 exception bits 32 through 47.

LQ:  RT,DQ(RA),PT

"PT" is an ORed mask of pointer type integrity checks to set AS/400
exception bit 41:

B'1000' = system pointer
B'0100' = instruction pointer
B'0010' = space pointer
B'0001' = data pointer

SELII: RT,IA,IB,XBI,rc
SELIR: RT,IA,RB,XBI,rc
SELRI: RT,RA,IB,XBI,rc
SELRR: RT,RA,RB,XBI,rc

The SELxx instructions test the AS/400 exception bit (32 through 47) named
in operand 4: if on, copy operand 2 into operand 1; if off, copy operand 3
into operand 1.  "IA" and "IB" are 5-bit signed immediate values, value
range -16 through +15.  "RA" and "RB" are general purpose registers.  "XBI"
is a 4-bit index into the sixteen AS/400 exception bits 32 through 47.  (In
other words, add 32 to the "XBI" 4-bit value.)

For example:

LQ 24,0X1E50(30),6
SELRI 26,25,0,41

This means,

LQ:  Copy the quadword at effective address (GPR30 + x"1E50") into GPR24
and GPR25; if the pointer tag bit at effective address (GPR30 + x"1E50") is
on, AND if that quadword data is an instruction pointer (integrity check
B'0100') or a space pointer (integrity check B'0010'), then set on AS/400
exception bit 41; otherwise, set off AS/400 exception bit 41.

SELRI:  Test AS/400 exception bit 41; if on, then copy GPR25 into GPR26; if
off, then copy x"0000000000000000" into GPR26.