Re: [MI400] most efficient RISC instruction

[Dave McKenzie <davemck@xxxxxxxxxxxxx>]

The PowerPC Architecture: A specification for a new family of RISC processors
Second Edition (May 1994)
Morgan Kaufmann Publishers, Inc.
ISBN 1-55860-316-6

Larry's probably thinking of the "with update" family of instructions, e.g.:

<quote>
Load Doubleword with Update Indexed  X-form

  ldux    RT,RA,RB

EA <- (RA) + (RB)
RT <- MEM(EA, 8)
RA <- EA

Let the effective address (EA) be the sum (RA)+(RB).  The doubleword in storage 
addressed by EA is loaded into RT.

EA is placed into register RA.

If RA=0 or RA=RT, the instruction form is invalid.

This instruction is defined only for 64-bit implementations.  Using it on a 
32-bit implementation will cause the system illegal instruction error handler 
to be invoked.

Special Registers Altered
  None
</quote>

--Dave



On Tuesday 25 June 2002 08:54 am, Steve Richter wrote:
> -----Original Message-----
> From: mi400-admin@midrange.com [mailto:mi400-admin@midrange.com]On
> Behalf Of Larry Loen
>
> >There actually are several "load with increment the pointer" instructions
> >and "store with increment the pointer instructions."
> >
> >Look 'em up!
>
> Where ???
>
> Steve Richter