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I'll offer another hypothesis. This one is based on a little more on research. But admitedly, only a theory. One component of IBM systems is known as the "system clock". It provides a signal that defines a base Mhz frequency used by other components, including the CPU. Actually, RAM, cache, bus, and I/O processor speed may all be synchronized with it. The PowerPC and other components use a circuit known as a "phase-lock-loop" (PLL) which synchronizes the various components and subsystems with the system clock. The CPU has a maximum recommended MHZ frequency, but can actually be configured to run at some multiple of the system clock. The ratio between system clock and CPU speed can range from one-to-one (1:1) up through ten-to-one (10:1). Some processors don't support that wide of a range. For example, a processor may have a maximum recommended speed of 200 Mhz and support PLL ratios of 1:1 - 4:1. If the system clock is set at 50 Mhz, and the PLL ratio is set at 1:1, then the CPU runs at 50 Mhz. If the system clock is set at 50 Mhz and the PLL ratio is configured at 4:1, then the CPU runs at 200 Mhz. Most of this information is a synopsis of my understanding of documents that can be found at www.chips.ibm.com, but you can also go to www.ibm.com and do a search on SYSCLK, PLL, system clock, etc. My theory is that Rochester uses the PPL configuration ratio to "gear down" the CPU from its maximum recommended Mhz rating. Nathan. +--- | This is the Midrange System Mailing List! | To submit a new message, send your mail to MIDRANGE-L@midrange.com. | To subscribe to this list send email to MIDRANGE-L-SUB@midrange.com. | To unsubscribe from this list send email to MIDRANGE-L-UNSUB@midrange.com. | Questions should be directed to the list owner/operator: david@midrange.com +---
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