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  1.  Home
  2. MI400
  3. November 1999

optimizing RISC

  • Subject: optimizing RISC
  • From: Gene Gaunt <issgg@xxxxxxx>
  • Date: Fri, 26 Nov 1999 20:07:37 -0700
 
Does PowerRC re-order instructions at execution?  If so, is comparing RISC 
disassemblies between OPM and ILE a reliable arbiter of efficiency or not?

Can the ILE compilers advise the translator on things like, "this branch 
condition will probably test true more often than false" or "execution at 
this branch target can overlap with another instruction"?  If so, might an 
"NMI programmer" write better optimized code?

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