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  2. MI400
  3. March 2003

Re: MI Entry Points

I notice the same oddity on V5R1.  MI program begin execution on
instruction 1, regardless if the external entry point isn't instruction 1.

CPYNV X, 0;
BRK "AAA";
CPYNV X, 1;
BRK "BBB";
CPYNV X, 2;
ENTRY  E  (L)  EXT;
CPYNV X, 3;
BRK "CCC";
CPYNV X, 4;
RTX *;
DCL DD X AUTO BIN(4);

The debug breakpoint sequence is AAA, BBB, CCC.

Why is it not CCC only?

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