POWER5

I was reading a great article in iSeries NEWS by Dr. Soltis about the POWER
processors (http://www.iseriesnetwork.com/Article.cfm?ID=15238). There
seems to be great things in store with the POWER5 line due out in 2004:

"POWER5, POWER6, and Beyond


Advances in semiconductor technologies have made it possible to add new
functions, and even whole new architectures, to our microprocessors. An
ongoing question for processor designers is how to use all of the
transistors that can be packaged on a single chip.


The POWER5 microprocessor is expected to appear in 2004. Like POWER4, it
will have two processors per chip and will support the multiple
architectures just discussed. In addition, it will support what IBM calls
"Fast Path." POWER5 will be able to directly execute some common software
tasks that are currently found in operating systems.


Instead of using a sequence of instructions to perform a common function,
the operating system will use a single instruction that causes the entire
function to be performed by the POWER5 microprocessor hardware. Examples of
these common functions include TCP/IP processing, communications
message-passing operations, and virtual memory subsystem operations, to
name a few. The interfaces to all of these silicon accelerators will be
open so that other operating systems, for example Linux, can take advantage
of them.


Another new feature in POWER5 will be simultaneous multithreading (SMT).
The idea behind SMT is to share the processor hardware on a chip among
multiple threads in a multiprogrammed workload. In this way, a single
processor on the chip can sometimes act as two processors.


The star family of microprocessors already supports a form of
multithreading. Each star family chip contains two complete sets of
processor registers to support two separate threads of execution. The
processor executes instructions out of one set of registers until a cache
miss occurs. Rather than waiting for the cache miss to finish, the
processor switches to the second set of registers and begins to execute
instructions from the second thread. This capability in the star family
increases the performance by about 30 percent over a single processor's
performance.


POWER4 did not implement multithreading because there were not enough
transistors on a chip to build two full processors and all the hardware
needed for multithreading. POWER5 has enough transistors to do both. The
goal of the POWER5 is to achieve a 100 percent increase in processor
performance using simultaneous multithreading. In other words, each
processor on the POWER5 chip will behave like two processors running at
full speed. Thus, each POWER5 chip will contain the equivalent of four
complete processors.


When POWER6 arrives in 2006, it is expected to extend the Fast Path idea to
even higher-level software such as DB2 and WebSphere processing. Again, all
of the silicon accelerator interfaces will be open, so other software
developers wil be able to take advantage of the improved performance.


The POWER4 microprocessor is the most sophisticated server processor on the
market. POWER5 promises to extend that lead, and the development of POWER6
is well underway. Even though it is often convenient to call the processor
architecture that these microprocessors support PowerPC, as we have just
seen, they actually support multiple architectures. Future generations of
POWER processors will likely support even more architectures. Sometimes
PowerPC really isn't just PowerPC."