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From: Leif Svalgaard <leif@leif.org>
> fair enough. It is interesting that all RISC architectures feature
> "complexity creep" with time. The original premise behind RISC
> was to ruthlessly remove complexity such that each instruction
> was as barebones as possible thereby allowing cheap and
> fast hardware implementation.

in a sense the S/36 with its only 14 or so instructions was very
RISCy. Van den Poel has shown that you can get away with a
VRISC instruction set containing only ONE instruction.




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