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I'm actually somewhat surprised by that performance difference. I would
expect such a difference in x86 architecture with a BCD number (close
approx to packed) since there is no native math opcodes for BCD. Integer
math is chip-level where BCD-math is process-driven. But I _thought_ one
of the mainframe and i-specific things on the power chip was hardware
instructions for packed math. Is it possible that the MI math opcodes
don't generate the "correct" Power instructions?

-Walden


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