Re: How are CPU Speed and Overall CPW Related?

----- Original Message -----
From: Nathan M. Andelin <nathanma@haaga.com>
To: <MIDRANGE-L@midrange.com>
Sent: Thursday, May 03, 2001 9:06 AM
Subject: Re: How are CPU Speed and Overall CPW Related?


> > From: "Leif Svalgaard" <leif@leif.org>
>
> > The loop the program is executing is so short (about 20 instructions)
that
> > it doesn't matter how large the cache is. No if there is no cache at all,
> > that might be different.
>
> Let's consider the difference between the 2 systems:
>
> 170-2290:
>    Processor: Northstar 200 Mhz.
>    L2 Cache: N/A
>    RAM: 320 MB
>
> 170-2385
>    Processor: Northstar 252 Mhz
>    L2 Cache: 4MB
>    RAM: 1 GB
>
> If not cache, then what would account for a performance improvement of 11
> times?  Both systems were doing very little other work at the time.  The
> work is entirely CPU bound.

From: . http://www.midrangecomputing.com/mc/articles/19980903.htm
       The Northstar processor used in the AS/400 family comes in three
speeds: 200, 252, and 262 MHz. They can be equipped with either 4 or 8 MB of
L2 cache memory, twice as much as Apache had. The Northstar has 64 KB of
on-chip (L1) data cache memory and another 64 KB of instruction cache. This
is same amount that was put into the Apache chip.
       The slowest Northstar chip is used in four of the 170 Invaders. Three
of the four 200-MHz Northstars are geared down to have the same exact
performance as last spring's 170 models using the 100-MHz Apache chip. (IBM
is doing this for marketing reasons, not technical ones. The 170s using the
slowest Northstars easily have five times as much raw processing power as IBM
is letting customers get at.) The 252-MHz Northstar is used in the new
high-end 170 Invader, which offers somewhat better performance than the
125-MHz Apache-based 170s they replace, although, again, even this is much
less power than is really under the hood. The 262-MHz Northstars are used in
the 650 systems and the S40 servers, and they are going full tilt boogie, no
holds barred.

----

The point is that they both have an L1 cache of 64K. More than big enough to
hold the entire loop
and its data. Therefore, the L2 cache doesn't matter.






+---
| This is the Midrange System Mailing List!
| To submit a new message, send your mail to MIDRANGE-L@midrange.com.
| To subscribe to this list send email to MIDRANGE-L-SUB@midrange.com.
| To unsubscribe from this list send email to MIDRANGE-L-UNSUB@midrange.com.
| Questions should be directed to the list owner/operator: david@midrange.com
+---